What are timing constraints?

In synchronous designs, the logic circuit can be described in RTL (Register Transfer Level).

The entire design can be visualized as a set of flip-flops and combinational logic.

For each flip-flop the library vendor (based on the technology) provides setup and hold constraints on the signal capturing pins w.r.t the clock pin. STA majorly checks whether for all the flip-flops present in the design, the setup and hold constraints are met.

Any synchronous design will have atleast one clock that captures/launches data into/outof the flip flops respectively.

The constraints that needs to be defined includes the clock period and its waveform (duty cycle).