What are timing constraints?

In synchronous designs, the logic circuit can be described in RTL (Register Transfer Level).

The entire design can be visualized as a set of flip-flops and combinational logic.

For each flip-flop the library vendor (based on the technology) provides setup and hold constraints on the signal capturing pins w.r.t the clock pin. STA majorly checks whether for all the flip-flops present in the design, the setup and hold constraints are met.

Any synchronous design will have atleast one clock that captures/launches data into/outof the flip flops respectively.

The constraints that needs to be defined includes the clock period and its waveform (duty cycle).

What is Static Timing Analysis

Static timing analysis (will be referred to as STA hence forth) is a technique in Application Specific Integrated Circuit implementation using which, the implemented logic circuit is validated against a set of timing constraints.

STA is carried out at different implementation Phases.
The following are the different implementation Phases:

1. HDL coding.
2. Synthesis.
3. DFT insertion.
4. Placement.
5. Routing.

Static timing analysis is used as a measure of how best the implementation achieves the required timing constraints.