What is a false path?

A false path, as its name denotes is a timing path not required to meet its timing constraints for the design to function properly.

In general all timing paths those are launched by a valid startpoint and captured by a valid endpoint impose setup and hold constraints. If the functionality of the design is such that the timing constraints need not be met on the path, it is a false path.

Every false path needs to be informed to the STA tool. As the STA tool considers every path that originates at a valid startpoint and ends on a valid endpoint as a valid timing path that needs to be met.

A situation where the design results in false paths is:
There are two 2 input muxes in a design. Both of which are selected by a common select line.


If you consider the signal B to be launched by a flop and Y to be captured by another flop, in no situation, there will be valid funtional path between B and Y.
Reason: Assume the muxes select signal at top side when the select line is 0 and the bottom signal when select line is 1. When the select line is 0, B is selected by mux 1, but the mux 1 output (D) will not be selected by mux 2. But the static timing analysis tool will not consider this as an invalid path, it just looks for valid timing arcs, an there is a timing arc from B input to output of the first mux and then to the Y signal through the second mux.

This is just a simple example of a false path. There can be many paths of this type in a large design. But, we cannot find each and every path and declare it as false. If this type of path is found in a clock muxing logic, then declaring a false path (I think set_disable_timing might be required for the paths in clock logic) through B and Y would be useful. If this type of path is found in a critical path of design, then it will be very useful to add a false path.

When functional ports are multiplexed with test logic, the input and output delays added on these ports would also show up many false paths.

If possible (timing is not critical and area is not critical), optimizing a false path is of no harm compared to declaring a functionally necessary path as a false path by mistake.

What is a timing path - Startpoint and endpoint

Any given timing path need to begin from a valid startpoint and end on a valid endpoint.
The following are valid startpoints:

• A primary input port.
• Capturing pin of a sequential cell (D pin of a flop, a latch or synchronous reset/set pins of a reset/set flop).

The following are valid endpoints:

• A primary output port.
• Launching pin of a sequential cell (CK pin of a flop or EN pin of a latch).

As evident from the number of start and end point types given above, any design with atleast two sequential cells, there can be 4 types of timing paths.

• Input to Register - Starting on a primary input port and ending on a capturing pin of a register
• Register to output - Starting on a launching pin of a flop and ending on an output port.
• Register to Register - Starting on a launching pin of a flop and ending on a capturing pin of a register
• Input to Output - Starting on a primary input port and ending on an output port.

Any valid timing path should be one of the above types.

There are several other types given by tools such as default, macro pins as startpoint and endpoint, which adds one additional startpoint type and one additional endpoint type and corresponding combinations of the timing paths. But, a macro in general can be considered as a register with many endpoints (input ports) and possibly many start points (clock pins).

What are timing constraints?

In synchronous designs, the logic circuit can be described in RTL (Register Transfer Level).

The entire design can be visualized as a set of flip-flops and combinational logic.

For each flip-flop the library vendor (based on the technology) provides setup and hold constraints on the signal capturing pins w.r.t the clock pin. STA majorly checks whether for all the flip-flops present in the design, the setup and hold constraints are met.

Any synchronous design will have atleast one clock that captures/launches data into/outof the flip flops respectively.

The constraints that needs to be defined includes the clock period and its waveform (duty cycle).

What is Static Timing Analysis

Static timing analysis (will be referred to as STA hence forth) is a technique in Application Specific Integrated Circuit implementation using which, the implemented logic circuit is validated against a set of timing constraints.

STA is carried out at different implementation Phases.
The following are the different implementation Phases:

1. HDL coding.
2. Synthesis.
3. DFT insertion.
4. Placement.
5. Routing.

Static timing analysis is used as a measure of how best the implementation achieves the required timing constraints.